US 12,469,569 B2
Smart erase inhibit
Ming Wang, Shanghai (CN); Liang Li, Shanghai (CN); and Wei Li, Shanghai (CN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Nov. 27, 2023, as Appl. No. 18/519,426.
Prior Publication US 2025/0174286 A1, May 29, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/0433 (2013.01); G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a control circuit configured to connect to a memory structure having NAND strings having memory cells, the control circuit configured to:
apply a first erase voltage to a plurality of bit lines during a first erase loop, wherein each bit line is connected to a group of NAND strings being erased, the bit lines include a first bit line connected to a first group of NAND strings being erased and a second bit line connected to a second group of NAND strings being erased;
verify each NAND string being erased in the first erase loop with respect to a first erase verify level and a second erase verify level that has a greater magnitude than the first erase verify level; and
responsive to a determination that at least one NAND string in the first group has a threshold voltage (Vt) above the second erase verify level and that all NAND strings in the second group have a Vt below the second erase verify level but at least one NAND string in the second group has a Vt above the first erase verify level:
apply a second erase voltage to the first bit line and a third erase voltage to the second bit line in a second erase loop that immediately follows the first erase loop, wherein the third erase voltage has a lower magnitude than the second erase voltage.