| CPC G11C 16/26 (2013.01) [G11C 5/063 (2013.01); G11C 16/0483 (2013.01); G11C 16/3481 (2013.01)] | 20 Claims |

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1. A memory apparatus, comprising:
memory cells configured to retain a threshold voltage corresponding to data states and disposed in memory holes coupled to bit lines and grouped into blocks; and
a control means coupled to the bit lines and configured to:
determine an amount of the memory cells of one of the blocks that are programmed based on an electrical current consumed by the memory apparatus during a fourth period of time of a read operation in which selected ones of the bit lines are ramped up to a bit line voltage,
adjust at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed, and
utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the data states in the read operation.
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