US 12,469,565 B2
Fast bit erase for upper tail tightening of threshold voltage distributions
Sheyang Ning, San Jose, CA (US); Lawrence Celso Miranda, San Jose, CA (US); and Tomoko Ogura Iwasaki, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 13, 2024, as Appl. No. 18/604,276.
Application 18/604,276 is a continuation of application No. 17/833,466, filed on Jun. 6, 2022, granted, now 11,961,566.
Claims priority of provisional application 63/224,263, filed on Jul. 21, 2021.
Prior Publication US 2024/0221841 A1, Jul. 4, 2024
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 16/3481 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising:
a first data line;
a first pillar coupled with the first data line;
a second data line;
a second pillar coupled with the second data line; and
a plurality of wordlines coupled with the first pillar and the second pillar; and
control logic operatively coupled with the memory array, the control logic to perform operations comprising:
causing the plurality of wordlines to be discharged after a program pulse is applied to program one or more memory cells coupled with a selected wordline of the plurality of wordlines;
causing a supply voltage to be applied to the second data line to cause a voltage of the second pillar to float;
causing a ground voltage to be applied to the first data line to inhibit soft erase associated with the selected wordline via the first pillar;
causing a first subset of unselected wordlines of the plurality of wordlines located below the selected wordline to remain discharged;
causing the selected wordline and a second subset of the unselected wordlines located above the selected wordline to be charged to boost channel voltages; and
causing, after boosting the second subset of the unselected wordlines, one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline.