US 12,469,564 B2
Memory device and operating method of the memory device
Nam Cheol Jeon, Icheon-si (KR); and Chang Beom Woo, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 31, 2024, as Appl. No. 18/428,275.
Claims priority of application No. 10-2023-0122267 (KR), filed on Sep. 14, 2023.
Prior Publication US 2025/0095747 A1, Mar. 20, 2025
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/0433 (2013.01); G11C 16/24 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first select transistor, a memory cell, and a second select transistor coupled in series between a source line and a bit line; and
a peripheral circuit configured to perform an erase operation on the memory cell,
wherein the peripheral circuit is configured to, during the erase operation:
apply an erase voltage to the source line and the bit line and a first pass voltage to a word line coupled to the memory cell at a first time,
apply a turn-on voltage to a first select line coupled to the first select transistor and a second select line coupled to the second select transistor at a second time before a level of the erase voltage applied to the source line and the bit line increases to a target level,
erase the memory cell by maintaining the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage applied to the source line and the bit line equals the target level, and
erase the memory cell by reducing a voltage difference between the memory cell and the word line at a fourth time after the third time.