US 12,469,563 B2
Serial-gate transistor and nonvolatile memory device including the same
Cheonan Lee, Suwon-si (KR); Kiwhan Song, Suwon-si (KR); Gyosoo Choo, Suwon-si (KR); and Sukkang Sung, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 10, 2023, as Appl. No. 18/120,244.
Claims priority of application No. 10-2022-0098804 (KR), filed on Aug. 8, 2022.
Prior Publication US 2024/0046994 A1, Feb. 8, 2024
Int. Cl. G11C 16/08 (2006.01); G11C 16/14 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC G11C 16/14 (2013.01) [G11C 16/08 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device, comprising:
a plurality of memory blocks;
a plurality of pass transistor blocks, each pass transistor block of the plurality of pass transistor blocks comprising a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks, each serial-gate transistor of the plurality of serial-gate transistors comprising:
a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate; and
a plurality of gates that are sequentially arranged in the horizontal direction in the gate region above the semiconductor substrate,
wherein the plurality of gates are electrically decoupled from each other,
wherein each gate of the plurality of gates is directly coupled to a corresponding block selection signal of a plurality of block selection signals, and
wherein the plurality of gates are controlled independently of each other.