| CPC G11C 16/08 (2013.01) | 16 Claims |
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1. A semiconductor device comprising:
a memory cell array comprising a first memory string that is connected to a first drain selection line and a second memory string that is connected to a second drain selection line;
a control circuit configured to generate a first switch control signal and a second switch control signal based on an address signal;
a first switch disposed in a direction corresponding to the first drain selection line and configured to connect a global word line with one end of a local word line or disconnect the global word line from the one end of the local word line based on the first switch control signal; and
a second switch disposed in a direction corresponding to the second drain selection line and configured to connect the global word line with the other end the local word line or disconnect the global word line from the other end of the local word line based on the second switch control signal,
wherein the global word line is selected and driven or is unselected and driven, and the local word line is connected to the first memory string and the second memory string in common,
when the global word line is selected and driven, the first switch connects the global word line with the one end of the local word line and the second switch connects the global word line with the other end of the local word line.
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