US 12,469,556 B2
Semiconductor device and operating method of semiconductor device
Chang Hyun Han, Gyeonggi-do (KR); and Moon Soo Sung, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 6, 2023, as Appl. No. 18/296,373.
Claims priority of application No. 10-2022-0165604 (KR), filed on Dec. 1, 2022.
Prior Publication US 2024/0185920 A1, Jun. 6, 2024
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0433 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a cell array including memory cells connected to local word lines;
an operation voltage supplying circuit that applies a read voltage or a pass voltage to global word lines; and
a well bias supplying circuit that, during a read operation, applies a well bias having a negative level to a well region of a pass transistor connected to a selected local word line, in a discharge period in which unselected local word lines are discharged,
wherein the well bias supplying circuit applies the well bias having a negative level to the well region in an equalizing period in which a voltage level of the selected local word line and a voltage level of each of the unselected local word lines are equalized.