| CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4093 (2013.01); G11C 11/54 (2013.01)] | 6 Claims |
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1. A method for controlling a NAND flash memory to complete neural network operation, comprising the following steps:
S0: providing a NAND flash memory, wherein the NAND flash memory comprises multiple memory blocks and multiple page buffers, the memory block comprises multiple synaptic strings, multiple bit lines, and multiple word lines, the synaptic string comprises multiple memory cells connected in series, the synaptic strings are connected to the bit lines in one-to-one correspondence, the word line is connected to all the synaptic strings, the page buffer is connected to all the memory blocks, and one of the bit lines is merely connected to one of the page buffers;
S1: writing weight data into the memory cell according to a relationship between the weight data and feature data;
S2: applying a target voltage to the memory cell by the word line; and
S3: sensing, by the page buffer, a current of the memory block, to obtain a convolution result; and
the method further comprising a calibration step, wherein the calibration step comprises:
by using a memory cell with known weight data and feature data as a reference unit, calibrating the sensing time of the page buffers with reference to a current of the reference unit that is sensed by a corresponding one of the page buffers.
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