US 12,469,545 B2
Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
Kedar Janardan Dhori, Ghaziabad (IN); Promod Kumar, Greater Noida (IN); Nitin Chawla, Noida (IN); Harsh Rawat, Faridabad (IN); and Manuj Ayodhyawasi, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 20, 2023, as Appl. No. 18/137,261.
Claims priority of provisional application 63/345,618, filed on May 25, 2022.
Prior Publication US 2023/0410892 A1, Dec. 21, 2023
Int. Cl. G11C 7/04 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 8/08 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 5/147 (2013.01); G11C 7/04 (2013.01); G11C 8/08 (2013.01)] 42 Claims
OG exemplary drawing
 
1. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line connected to the memory cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row, wherein the word line driver circuit has a power supply node connected to receive an adaptive supply voltage having a voltage level that is modulated dependent on integrated circuit process and/or temperature conditions;
a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines for an in-memory compute operation; and
a column processing circuit including a first read circuit coupled to each first bit line, wherein each first read circuit comprises:
a first current mirroring circuit configured to mirror a first read current on the first bit line to generate a first mirrored read current; and
a first integration capacitor configured to integrate the first mirrored read current to generate a first output voltage;
wherein the adaptive supply voltage and configuration of the first current mirroring circuit inhibits drop of a voltage on the first bit line below a bit flip voltage during the simultaneous actuation of the plurality of word lines for the in-memory compute operation.