| CPC G11C 11/4091 (2013.01) [G11C 5/147 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
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9. A sense amplifier, comprising:
a first transistor coupled between a first node configured to receive an activation signal, a first digit line, and a second digit line, wherein the first digit line is configured to receive a first charge from one or more memory cells corresponding to the sense amplifier for sensing, the second digit line is configured to receive a second charge from the one or more memory cells and is complementary to the first digit line;
a second transistor coupled between the first node, the first digit line, and a second digit line;
a third transistor coupled between a first gut node corresponding to the first digit line, a second gut node corresponding to the second digit line, and a second node configured to receive a strobe signal;
a fourth transistor coupled between the first gut node, the second gut node, and the second node; and
threshold voltage compensation circuitry configured to:
compensate for a threshold voltage offset between the third and fourth transistors during a voltage threshold compensation phase without using any threshold voltage offset between the first and second transistors;
pre-sense using the third and fourth transistors during a pre-sense phase; and
sense and latch using the first, second, third, and fourth transistors during a main sensing and latching phase after the pre-sense phase.
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