US 12,469,538 B2
Resistance change memory, memory device, and memory system
Haruko Takahashi, Kanagawa (JP); Masami Kuroda, Kanagawa (JP); and Hiroyuki Tezuka, Tokyo (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/258,405
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Dec. 16, 2021, PCT No. PCT/JP2021/046488
§ 371(c)(1), (2) Date Jun. 20, 2023,
PCT Pub. No. WO2022/145251, PCT Pub. Date Jul. 7, 2022.
Claims priority of application No. 2020-218396 (JP), filed on Dec. 28, 2020.
Prior Publication US 2024/0038286 A1, Feb. 1, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1653 (2013.01); G11C 11/1697 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A resistance change memory, comprising:
a memory cell including a resistance change element;
a write drive unit configured to:
apply a write voltage to the memory cell; and
perform, based on the applied write voltage, a writing operation of data to the memory cell;
a well region that comprises an element constituting the write drive unit;
a write control unit configured to:
output a write control signal based on the write voltage; and
control the writing operation based on the write control signal; and
a well potential adjustment unit configured to adjust a well potential of the well region based on the write voltage.