US 12,469,536 B2
Memory and electronic device
Qing Qin, Shenzhen (CN); Xue Zhou, Shenzhen (CN); and Xi Liu, Shenzhen (CN)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on May 25, 2023, as Appl. No. 18/323,702.
Application 18/323,702 is a continuation of application No. PCT/CN2020/132884, filed on Nov. 30, 2020.
Prior Publication US 2023/0298648 A1, Sep. 21, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01F 10/32 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01)
CPC G11C 11/161 (2013.01) [G11C 11/1655 (2013.01); H01F 10/3286 (2013.01); H10B 61/20 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory, comprising a plurality of storage units and bit lines distributed in an array in a storage area of the memory, wherein:
each of the plurality of storage units comprises a transistor and a magnetic tunnel junction (MTJ) element connected to the transistor;
the MTJ element is disposed on a current transmission path between a source or a drain of the transistor and a bit line, the MTJ element comprises a pinning layer, a reference layer, a tunneling layer, and a free layer that are stacked in sequence, and a magnetization direction of the pinning layer is parallel to a stacking direction of layers in the MTJ;
the memory further comprises a first magnetic structure disposed on the current transmission path and in direct contact with the MTJ element; and
an included angle between a magnetization direction of the first magnetic structure and the magnetization direction of the pinning layer is (90°, 180°].