| CPC G11C 7/222 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1063 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
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1. A calibration apparatus of a memory device, comprising:
an impedance, configured to generate a comparison voltage;
a strong-arm comparator, comprising:
a non-inverting input received a reference voltage;
an inverting input end received the comparison voltage, the strong-arm comparator compares the reference voltage and the comparison voltage to generate a differential comparison result, latches the differential comparison result and correspondingly generates a latch signal and an inverted latch signal;
a first output terminal, outputting the latch signal; and
a second output terminal, outputting the inverted latch signal;
a logic circuit, coupled to the strong-arm comparator to generate a comparison result signal according to the latch signal and the inverted latch signal; and
a calibration controller, wherein the calibration controller implements an impedance calibration in the memory device according to the comparison result signal,
wherein the logic circuit comprises:
a logic subcircuit, wherein a first input terminal of the logic subcircuit is coupled to the first output terminal of the strong-arm comparator, a second input terminal of the logic subcircuit is coupled to the second output terminal of the strong-arm comparator, and an output terminal of the logic subcircuit generates a clock signal; and
a data flip-flop comprises a data input terminal, a clock receiving terminal and a data output terminal, wherein the first output terminal of the strong-arm comparator is coupled to the data input terminal, the output terminal of the logic subcircuit is coupled to the clock receiving terminal, and the data flip-flop generates the comparison result signal at the data output terminal according to the latch signal and the clock signal generated by the logic subcircuit.
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