US 12,469,527 B2
In situ delay measurements on integrated circuits using live data and pulse width modulation
Karen Darbinyan, Pleasanton, CA (US); Yervant Zorian, Santa Clara, CA (US); Grigor Khachatryan, Yerevan (AM); and Karen Melkonyan, Ararat (AM)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Sep. 6, 2023, as Appl. No. 18/462,380.
Prior Publication US 2025/0078882 A1, Mar. 6, 2025
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03K 5/15 (2006.01)
CPC G11C 7/1066 (2013.01) [G11C 7/222 (2013.01); H03K 5/15 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
digital circuitry; and
a plurality of property monitors that monitor properties of the digital circuitry; wherein the plurality of property monitors generate pulses having widths that are a function of the properties, the property monitors are delay monitors that monitor delays of data signals from the digital circuitry, the delay monitors generate the pulses having the widths determined by the delays, and the delay monitors each comprise:
a first counter that counts a number c1 of events that overlap with the pulses, wherein the events are distributed in time relative to a clock signal that clocks the data signal; and
a second counter that counts a total number c2 of events, wherein the delay is estimable as a function of (c1/c2).