US 12,469,522 B2
Semiconductor device including charge retention node
Woo Cheol Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 16, 2024, as Appl. No. 18/413,596.
Claims priority of application No. 10-2023-0118766 (KR), filed on Sep. 7, 2023.
Prior Publication US 2025/0087248 A1, Mar. 13, 2025
Int. Cl. G11C 16/28 (2006.01); G11C 5/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC G11C 5/063 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); G11C 16/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
first and second transistors disposed on a substrate,
wherein the first transistor comprises:
first and second source/drain regions;
a first channel region between the first and second source/drain regions;
a first gate electrode over the first channel region; and
a charge retention node between the first channel region and the first gate electrode, and
wherein the second transistor comprises:
third and fourth source/drain regions, a portion of the third source/drain region being connected to the charge retention node;
a second channel region between the third and fourth source/drain regions; and
a second gate electrode over the second channel region.