| CPC G09G 3/3291 (2013.01) [H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01)] | 19 Claims |

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1. A display device, comprising:
a display panel including a light emitting element, a driving transistor having a first node being a gate electrode, a second node being a drain electrode, and a third node being a source electrode, and configured to provide a driving current to the light emitting element, a plurality of switching transistors configured to control an operation of the driving transistor, and a storage capacitor having first electrode and second electrode;
a gate driving circuit configured to supply a plurality of scan signals to the display panel;
wherein the plurality of switching transistors include;
a first switching transistor turned on by a first scan signal, the first switching transistor configured to diode-connect the first node and the third node;
a second switching transistor turned on by a second scan signal, the second switching transistor configured to supply a data voltage or a bias voltage to the second node;
a third switching transistor turned on by a light emitting signal, the third switching transistor configured to supply a high potential driving voltage from a fourth node connected to the first electrode of the storage capacitor to the second node;
a fourth switching transistor turned on by the light emitting signal, the fourth switching transistor configured to form a current path between the driving transistor and the light emitting element; and
a fifth switching transistor turned on by a third scan signal, the fifth switching transistor configured to supply a first voltage to the first node,
wherein the first electrode of the storage capacitor is connected to the fourth node,
wherein the second electrode of the storage capacitor is connected to the first node,
wherein the display panel including a plurality of subpixels, driven in a high-speed mode at a high driving frequency and in a low-speed mode at a low driving frequency that is less than the high driving frequency,
wherein a data voltage is supplied to the display panel during a first period and the bias voltage is supplied to the driving transistor in a second period in the low-speed mode, and
wherein the second period is a period after the first period and before a light emitting period of the light emitting element.
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