US 12,469,463 B2
Display device and electronic device
Takayuki Ikeda, Atsugi (JP); Hidetomo Kobayashi, Isehara (JP); Hideaki Shishido, Atsugi (JP); Kiyotaka Kimura, Isehara (JP); Takashi Nakagawa, Sagamihara (JP); and Kosei Nei, Yokohama (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Oct. 16, 2023, as Appl. No. 18/380,221.
Application 18/380,221 is a continuation of application No. 17/887,708, filed on Aug. 15, 2022, granted, now 11,798,491.
Application 17/887,708 is a continuation of application No. 17/055,285, granted, now 11,423,844, issued on Aug. 23, 2022, previously published as PCT/IB2019/053804, filed on May 9, 2019.
Claims priority of application No. 2018-095244 (JP), filed on May 17, 2018; application No. 2018-108416 (JP), filed on Jun. 6, 2018; and application No. 2018-159543 (JP), filed on Aug. 28, 2018.
Prior Publication US 2024/0062724 A1, Feb. 22, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3233 (2016.01); G09G 3/3275 (2016.01); G09G 5/377 (2006.01); H10D 30/67 (2025.01); H10K 59/127 (2023.01); G09G 3/36 (2006.01)
CPC G09G 3/3275 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 5/377 (2013.01); H10D 30/6755 (2025.01); H10K 59/1275 (2023.02); G09G 3/36 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0297 (2013.01); G09G 2340/12 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A display device comprising:
a display portion comprising pixels;
a gate driver circuit; and
a source driver circuit,
wherein the gate driver circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor in a first region,
wherein the source driver circuit comprises a fifth transistor positioned between the first transistor and the second transistor in the first region,
wherein the first transistor is adjacent to the fifth transistor in a first direction,
wherein the second transistor is adjacent to the fifth transistor, in the first direction,
wherein the third transistor is adjacent to the fifth transistor in a second direction perpendicular to the first direction, and
wherein the fourth transistor is adjacent to the fifth transistor in the second direction.