| CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); H03K 17/6871 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
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1. A gate driving circuit comprising a plurality of stages each comprising:
a first control circuit connected to a first voltage input terminal receiving a first voltage and a second voltage input terminal receiving a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node and a second control node;
a first output circuit connected to a first clock terminal and a third voltage input terminal receiving a third voltage, the first output circuit being configured to output a gate signal according to the voltage levels of the first control node and the second control node; and
a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a carry signal according to the voltage levels of the first control node and the second control node,
wherein the first control circuit comprises:
a first transistor connected to a first input terminal and the first control node, a gate of the first transistor being connected to the first input terminal; and
a second transistor connected to the first input terminal and the first control node, a gate of the second transistor being connected to a second input terminal,
wherein the second transistor comprises a first sub-transistor and a second sub-transistor that are connected in series, the first input terminal is connected to an output terminal of the second output circuit of a previous stage, and the second input terminal is connected to the output terminal of the second output circuit of a next stage,
wherein the second voltage is lower than the third voltage.
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