| CPC G09G 3/3266 (2013.01) [G09G 3/3225 (2013.01); G11C 19/287 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] | 15 Claims |
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1. A scan driver circuit, comprising multiple clock signal lines and multiple cascaded shift registers, wherein:
each of the shift registers comprises an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit;
the input sub-circuit is connected to a starting signal terminal, a first node and a first signal terminal, and the input sub-circuit is configured to write a signal at the starting signal terminal into the first node under the control of the signal at the first signal terminal;
the first control sub-circuit is connected to the first signal terminal, the first node and a second node, and the first control sub-circuit is configured to write the signal at the first signal terminal into the second node under the control of the signal at the first node;
the second control sub-circuit is connected to the first node, the second node, a second voltage terminal and a third signal terminal, and the second control sub-circuit is configured to write the signal at the second voltage terminal into the first node under the control of signals at the second node and the third signal terminal;
the output sub-circuit is connected to the first node, the second node, an output terminal, a second signal terminal and the second voltage terminal, and the output sub-circuit is configured to write the signal at the second signal terminal into the output terminal under the control of the signal at the first node, and is also configured to write the signal at the second voltage terminal into the output terminal under the control of the signal at the first node;
the second signal terminal and the third signal terminal of the same shift register are connected to different clock signal lines;
the clock signal lines comprise a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the shift registers comprise a first shift register and a second shift register connected in cascade; in the first shift register, the first signal terminal is connected to the first clock signal line, the second signal terminal is connected to the second clock signal line, and the third signal terminal is connected to the fourth clock signal line; in the second shift register, the first signal terminal is connected to the second clock signal line, the second signal terminal is connected to the first clock signal line, and the third signal terminal is connected to the third clock signal line;
the shift registers further comprise a fifth shift register and a sixth shift register, and the first shift register, the second shift register, the fifth shift register, and the sixth shift register are cascaded in sequence; in the fifth shift register, the first signal terminal is connected to the third clock signal line, the second signal terminal is connected to the fourth clock signal line, and the third signal terminal is connected to the second clock signal line; in the sixth shift register, the first signal terminal is connected to the fourth clock signal line, the second signal terminal is connected to the third clock signal line, and the third signal terminal is connected to the first clock signal line; and
the clock signal lines further comprise a fifth clock signal line and a sixth clock signal line, and the shift registers further comprise a third shift register and a fourth shift register, the first shift register, the second shift register, the third shift register, and the fourth shift register are arranged in sequence and connected in cascade; in the third shift register, the first signal terminal is connected to the fifth clock signal line, the second signal terminal is connected to the sixth clock signal line, and the third signal terminal is connected to the fourth clock signal line; in the fourth shift register, the first signal terminal is connected to the sixth clock signal line, the second signal terminal is connected to the fifth clock signal line, and the third signal terminal is connected to the third clock signal line.
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