US 12,469,460 B2
Display substrate and display device
Xuehuan Feng, Beijing (CN); and Yongqian Li, Beijing (CN)
Assigned to HEFEI BOE JOINT TECHNOLOGY CO., LTD, Hefei (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Appl. No. 18/247,464
Filed by HEFEI BOE JOINT TECHNOLOGY CO., LTD., Hefei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 23, 2022, PCT No. PCT/CN2022/100838
§ 371(c)(1), (2) Date Mar. 31, 2023,
PCT Pub. No. WO2023/245563, PCT Pub. Date Dec. 28, 2023.
Prior Publication US 2024/0363077 A1, Oct. 31, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3208 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising: a base substrate, and a gate driving circuit and a plurality of signal lines arranged on the base substrate; wherein
the plurality of signal lines comprise a first clock sub-signal line and a second clock sub-signal line which are independent of each other, wherein the first clock sub-signal line and the second clock sub-signal line are not connected to each other;
the gate driving circuit comprises a plurality of shift register units that are cascaded, each shift register unit of the plurality of shift register units that are cascaded comprises a first sub-unit and a blanking input sub-unit;
the first sub-unit comprises a first input circuit, a first output circuit, a first control circuit, and a third control circuit,
the blanking input sub-unit comprises a first transmission circuit, a selection control circuit, and a third input circuit;
the first input circuit is configured to control a level of a first node in response to a first input signal;
the first output circuit is configured to output a shift signal and a first output signal under control of the level of the first node;
the first transmission circuit is electrically connected with the first node and a fourth node, and is configured to control the level of the first node under control of a level of the fourth node or a first transmission signal;
the selection control circuit is configured to control a level of a third node using a second input signal in response to a selection control signal, and to maintain the level of the third node;
the third input circuit is connected with the third node, the fourth node, and the first clock sub-signal line, and is configured to transmit a first clock sub-signal provided by the first clock sub-signal line to the fourth node under control of the level of the third node to control the level of the fourth node and the first clock sub-signal line only provides the first clock sub-signal to the third input circuit;
the first control circuit is configured to control a level of a fifth node under control of the level of the first node and a second voltage;
the third control circuit is connected with the second clock sub-signal line and the fifth node, and is configured to control the level of the fifth node in response to a second clock sub-signal provided by the second clock sub-signal line and the second clock sub-signal line only provides the second clock sub-signal to the third control circuit;
wherein an orthographic projection of the first clock sub-signal line on the base substrate and an orthographic projection of the second clock sub-signal line on the base substrate are arranged side by side, and the first clock sub-signal provided by the first clock sub-signal line is the same as the second clock sub-signal provided by the second clock sub-signal line.