| CPC G09G 3/3241 (2013.01) [G09G 3/3258 (2013.01); G09G 2310/0245 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/0262 (2013.01); G09G 2320/0214 (2013.01)] | 19 Claims |
|
1. A method of setting a panel voltage applied to pixels of display panel, comprising:
setting a first reference voltage, a second reference voltage lower than the first reference voltage and higher than a panel default voltage, and a reference current;
applying the first reference voltage to the pixels;
obtaining a first measurement current by measuring a current of the display panel generated in response to the first reference voltage;
comparing the first measurement current with the reference current;
obtaining a second measurement current by measuring a current of the display panel generated in response to the second reference voltage when the first measurement current is greater than the reference current;
comparing the second measurement current with the reference current; and
obtaining a panel setting voltage based on the first reference voltage and the second reference voltage when the second measurement current is less than or equal to the reference current,
wherein each of the pixels comprises a first transistor generating a driving current based on a voltage of a second node and a third transistor diode-connecting the first transistor in response to a second gate signal,
wherein the first reference voltage and the second reference voltage are a gate-source voltage of the third transistor, and the gate-source voltage of the third transistor is a voltage difference between a gate electrode of the third transistor and a source electrode of the third transistor,
wherein each of the pixels further includes:
a second transistor including a second gate electrode receiving a first gate signal, a third electrode connected to a data line, and a fourth electrode connected to a first node;
a fourth transistor including a fourth gate electrode receiving a third gate signal, a seventh electrode receiving a first initialization voltage, and an eighth electrode connected to the second node;
a fifth transistor including a fifth gate electrode receiving an emission signal, a ninth electrode receiving a first power supply voltage, and a tenth electrode connected to the first node;
a sixth transistor including a sixth gate electrode receiving the emission signal, an eleventh electrode connected to a third node, and a twelfth electrode connected to a fourth node;
a seventh transistor including a seventh gate electrode receiving a fourth gate signal, a thirteenth electrode receiving a second initialization voltage, and a fourteenth electrode connected to the fourth node;
an eighth transistor including an eighth gate electrode receiving the fourth gate signal, a fifteenth electrode receiving a bias voltage, and a sixteenth electrode connected to the first node;
a storage capacitor including a seventeenth electrode receiving the first power supply voltage and an eighteenth electrode connected to the second node; and
a light emitting element including a nineteenth electrode connected to the fourth node and a twentieth electrode receiving a second power supply voltage lower than the first power supply voltage,
wherein the first transistor includes a first electrode connected to the first node, a first gate electrode connected to the second node, and a second electrode connected to the third node, and
wherein the third transistor includes a third gate electrode receiving the second gate signal, a fifth electrode connected to the third node, and a sixth electrode connected to the second node.
|