US 12,469,455 B2
Display device
Sehyuk Park, Yongin-si (KR); Hongsoo Kim, Yongin-si (KR); and Jin-Wook Yang, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Oct. 22, 2024, as Appl. No. 18/922,578.
Claims priority of application No. 10-2023-0142317 (KR), filed on Oct. 23, 2023.
Prior Publication US 2025/0131881 A1, Apr. 24, 2025
Int. Cl. G09G 3/3233 (2016.01); G09G 3/20 (2006.01)
CPC G09G 3/3233 (2013.01) [G09G 3/2003 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display device comprising:
a plurality of data lines arranged in a first direction;
a demultiplexer connected to the plurality of data lines;
a plurality of first gate lines arranged in a second direction;
a plurality of second gate lines arranged in the second direction; and
a plurality of pixels, each of which is connected to one corresponding data line among the plurality of data lines and one corresponding gate line among the plurality of first gate lines and the plurality of second gate lines, the plurality of pixels including a first group of pixels and a second group of pixels,
wherein the plurality of data lines includes a first group of data lines connected to the first group of pixels and a second group of data lines connected to the second group of pixels,
wherein a data signal is provided to the first group of pixels in a first sub-frame period of one frame period, and
wherein a data signal is provided to the second group of pixels in a second sub-frame period of the one frame period that is adjacent to the first sub-frame period,
wherein the demultiplexer includes a plurality of first control transistors connected to the first group of data lines in a one-to-one correspondence and a plurality of second control transistors connected to the second group of data lines in a one-to-one correspondence,
wherein in the first sub-frame period, a first control signal that controls a plurality of first control transistors has activation levels and inactivation levels alternating with one another, and a second control signal that controls a plurality of second control transistors has an inactivation level throughout an entirety of the first sub-frame period, and
wherein in the second sub-frame period, the second control signal has activation levels and inactivation levels alternating with one another, and the first control signal has an inactivation level throughout an entirety of the second sub-frame period.