| CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0233 (2013.01)] | 20 Claims |

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1. An array base plate, comprising:
a substrate;
a plurality of sub-pixels that are located on the substrate and arranged in array; and
a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines intersect with the plurality of data lines, each of the sub-pixels is located at a position limited by two adjacent gate lines and two adjacent data lines, and each of the sub-pixels comprises a pixel driving circuit and a light emitting device that are electrically connected; wherein the pixel driving circuit comprises:
a drive module electrically connected to a first node, a second node and an anode of the light emitting device, wherein the drive module is configured for conducting a path between the second node and the anode under control of a voltage of the first node, and generating a current in the path to make the light emitting device emit light; the second node is coupled to the first power signal line; and
a first control module electrically connected to a first control signal line, a second power signal line and the anode of the light emitting device, wherein the first control module is configured for transferring a second power signal transmitted by the second power signal line to the anode under control of a first control signal transmitted by the first control signal line, wherein the first control module comprises a third transistor;
wherein the pixel driving circuit further comprises an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected to the anode; the first power signal line comprises a first part and a second part that are electrically connected, the first part of the first power signal line and the first control signal line are arranged on a same layer, and the second part of the first power signal line and the auxiliary anode are arranged on a same layer, wherein the first part of the first power signal line and the second part of the first power signal line are located in different layers.
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