| CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01)] | 18 Claims |
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1. A pixel driving circuit, comprising a driving transistor, a first reset sub-circuit, a second reset sub-circuit, a light emitting control sub-circuit, a data writing circuit, a first energy storage element, and a second energy storage element,
wherein the first reset sub-circuit is configured to write an initialization voltage signal to a third node in response to a first reset signal, wherein the third node is a connection node between a second electrode of the driving transistor and a first end of the first energy storage element;
the second reset sub-circuit is configured to, in response to a second reset signal, turn it conductive between a gate of the driving transistor and a fourth node and reset the gate of the driving transistor and the fourth node, wherein the fourth node is a connection node among the first energy storage element, the second energy storage element and the second reset sub-circuit;
the data writing sub-circuit is configured to write a data voltage signal to the second energy storage element in response to a scanning signal; and
the light emitting control sub-circuit is configured to turn it conductive between a first electrode of the driving transistor and a power supply terminal in response to a first light emitting control signal, and transmit the data voltage signal to the gate of the driving transistor in response to a second light emitting control signal,
wherein the second reset sub-circuit comprises a second reset transistor and a third reset transistor,
wherein a gate of the second reset transistor is connected to a second reset signal line, a first electrode of the second reset transistor is connected to a reference voltage line, and a second electrode of the second reset transistor is connected to the fourth node; and
a gate of the third reset transistor is connected to the second reset signal line, a first electrode of the third reset transistor is connected to the gate of the driving transistor, and a second electrode of the third reset transistor is connected to the fourth node,
wherein the second reset transistor and the third reset transistor are both double-gate transistors, a first gate of the second reset transistor and a first gate of the third reset transistor are of a one-piece structure, and a second gate of the second reset transistor and a second gate of the third reset transistor are of a one-piece structure; and
the second reset signal line is connected to the first gate of the second reset transistor and the first gate of the third reset transistor through a second via, and is connected to the second gate of the second reset transistor and the second gate of the third reset transistor through a third via.
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