| CPC G09G 3/2096 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/028 (2013.01); G09G 2354/00 (2013.01)] | 15 Claims |
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1. A display device comprising:
a display panel including pixels;
a data driver configured to output data voltages to the pixels;
a gate driver configured to output a write gate signal to write the data voltages to the pixels having an inactivation level in a frame stop period;
a timing controller configured to control the data driver and the gate driver;
an emission driver configured to output an emission signal to the pixels; and
a voltage generator configured to apply a first bias voltage to first pixels to which the data voltages are written before the frame stop period among the pixels, and to apply a second bias voltage to second pixels, different from the first pixels and to which the first bias voltage is not applied, to which the data voltages are written after the frame stop period among the pixels,
wherein each of the pixels includes a driving transistor,
wherein the gate driver is configured to output a bias gate signal to the pixels,
wherein the first bias voltage is applied to the driving transistor of each of the first pixels in response to the bias gate signal,
wherein the second bias voltage is applied to the driving transistor of each of the second pixels in response to the bias gate signal,
wherein the timing controller is configured to maintain an output of the emission signal in the frame stop period,
wherein the timing controller is configured to maintain an output of the bias gate signal in the frame stop period, and
wherein a time between an activation timing of the bias gate signal and an activation timing of the emission signal is constant.
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