| CPC G09G 3/2092 (2013.01) [G09G 3/20 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/0267 (2013.01)] | 7 Claims |
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1. A scan drive circuit comprising:
a first thin-film transistor (hereinafter referred to as “the first transistor”) configured to send an input signal to a gate electrode of a second thin-film transistor (hereinafter referred to as “the second transistor”) when in “on” state;
the second transistor configured to output an input signal to an output scan signal line when in “on” state;
a third thin-film transistor (hereinafter referred to as “the third transistor”) configured to convert a gate voltage of the second transistor into a source voltage of the third transistor when in “on” state;
a fourth thin-film transistor (hereinafter referred to as “the fourth transistor”) configured to convert a scan output voltage of the output scan signal line into a voltage connected to a source of the fourth transistor when in “on” state;
a capacitor for bootstrapping;
a main scan signal line configured to apply an on/off control signal to the first transistor;
a DC power line connected to a drain electrode of the first transistor;
a sub-scan signal line configured to apply, as an input signal, a signal output from the second transistor when the second transistor is in “on” state;
a main scan inverted signal line configured to apply an inverted main scan signal, as an on/off control signal for the third transistor and the fourth transistor, to gate electrodes of the third transistor and the fourth transistor;
a second input signal line configured to apply an input signal to the fourth transistor; and
the output scan signal line configured to output a final scan signal output from the second transistor,
wherein the scan drive circuit is configured to:
enable stable operation even when the first transistor is a depletion-type thin-film transistor, by applying a main scan signal via a main scan signal line; and
prevent gate floating by controlling gate voltages of the third and fourth transistors through pairs of a main scan signal and an inverted main scan signal, each pair corresponding to a different group of output scan signal lines.
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