US 12,468,927 B2
Expandable neuromorphic circuit
Joon Young Kwak, Seoul (KR); Suyoun Lee, Seoul (KR); Inho Kim, Seoul (KR); Jong-Keuk Park, Seoul (KR); Kyeong Seok Lee, Seoul (KR); Jaewook Kim, Seoul (KR); Jongkil Park, Seoul (KR); YeonJoo Jeong, Seoul (KR); and Gyuweon Hwang, Seoul (KR)
Assigned to Korea Institute of Science and Technology, Seoul (KR)
Filed by KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, Seoul (KR)
Filed on Mar. 18, 2021, as Appl. No. 17/205,620.
Claims priority of application No. 10-2020-0142592 (KR), filed on Oct. 29, 2020.
Prior Publication US 2022/0138546 A1, May 5, 2022
Int. Cl. G06N 3/049 (2023.01); G06N 3/04 (2023.01); G06N 3/048 (2023.01); G06N 3/065 (2023.01); G11C 11/54 (2006.01)
CPC G06N 3/065 (2023.01) [G06N 3/049 (2013.01); G11C 11/54 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A neuromorphic circuit comprising:
a first neuron array including a plurality of neuron circuits generating a spike signal;
a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array;
a second synapse array including a plurality of second synapse circuits;
a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and
a control logic to generate the control signal;
wherein the first connecting block connects column lines in the first synapse array respectively to an equal number of column lines in the second synapse array,
wherein the first connecting block includes a plurality of switches for transmitting signals of input lines or output lines of the first synapse circuits in response to the control signal, each of the plurality of switches connecting a column line in the first synapse array to a column line in the second synapse array, and
wherein each of the plurality of switches includes complementary pass transistor logic (CPTL) that transmits a same signal level as a signal level in the column line in the first synapse array to the column line in the second synapse array.