US 12,468,926 B2
Circular buffering in neural network processor
Christopher L. Mills, Saratoga, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 10, 2021, as Appl. No. 17/344,900.
Prior Publication US 2022/0398440 A1, Dec. 15, 2022
Int. Cl. G06F 13/14 (2006.01); G06F 13/16 (2006.01); G06N 3/063 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 13/1673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural processor circuit, comprising:
a plurality of neural engine circuits, at least one of the neural engine circuits configured to perform at least convolution operations; and
a data processor circuit coupled to the at least one neural engine circuit, the data processor circuit including:
a circular buffer, and
a flow control circuit coupled to the circular buffer, the flow control circuit configured to generate a plurality of addressing parameters that defines wrapping of data in the circular buffer, wherein:
the circular buffer is configured to control data flow in the neural processor circuit by storing first data associated with the at least one neural engine circuit so that the first data is wrapped around in the circular buffer,
an addressing layout of the first data wrapped around in the circular buffer is defined by the plurality of addressing parameters, and
the plurality of addressing parameters comprises:
a first addressing parameter that determines a start address in the circular buffer for storing the first data; and
a second addressing parameter that determines an end address of a first segment of the first data in the circular buffer and a start address of a second segment of the first data in the circular buffer, the second segment following the first segment within the first data, the second segment preceding the first segment within the circular buffer.