US 12,468,904 B2
Accelerator for mathematical operations based on analog computing
Dimitrios Schoinianakis, Athens (GR)
Assigned to Nokia Technologies Oy, Espoo (FI)
Filed by Nokia Technologies Oy, Espoo (FI)
Filed on Apr. 24, 2024, as Appl. No. 18/645,233.
Claims priority of application No. 23171077 (EP), filed on May 2, 2023.
Prior Publication US 2024/0370673 A1, Nov. 7, 2024
Int. Cl. G06G 7/04 (2006.01); G06G 7/16 (2006.01)
CPC G06G 7/04 (2013.01) [G06G 7/16 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computation device comprising:
one or more input device terminals caused to receive respective analog input signals of the device;
one or more output device terminals caused to receive respective analog output signals of the device;
one or more rows of analog cells, wherein an analog cell comprises an input cell terminal and an output cell terminal, wherein the analog cell is caused to generate, at the output cell terminal, an output analog signal whose amplitude is a product of a multiplication coefficient by an amplitude of the analog input signal received at the input cell terminal, wherein input cell terminals in a row are connected to a same input device terminal; and
a network of switches caused to selectively interconnect output cell terminals of the analog cells and selectively connect the output cell terminal of each of the analog cells to an output device terminal.