US 12,468,874 B2
Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection
William Alexander Hughes, San Jose, CA (US); Sandeep Srinivasan, Palo Alto, CA (US); and Rohit Uday Suvarna, Jersey City, NJ (US)
Assigned to VERIFAI INC., Palo Alto, CA (US)
Filed by VERIFAI INC., Palo Alto, CA (US)
Filed on Nov. 18, 2022, as Appl. No. 17/989,805.
Claims priority of provisional application 63/280,987, filed on Nov. 18, 2021.
Prior Publication US 2023/0153513 A1, May 18, 2023
Int. Cl. G06F 30/3308 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01); G06N 20/00 (2019.01)
CPC G06F 30/3308 (2020.01) [G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor; and
a memory storing instructions thereon that, when executed by the processor, cause the processor to:
simulate a circuit design according to a set of simulation runs;
provide, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation runs;
receive an output in response to the machine learning network processing the functional coverage results, wherein the output comprises:
an indication of a near miss event associated with the functional coverage results; and
a recommended set of simulation parameters; and
simulate the circuit design based on the recommended set of simulation parameters, wherein simulating the circuit design based on the recommended set of simulation parameters comprises generating a set of component signals associated with triggering the near miss event.