US 12,468,862 B2
Partitioned cryptographic protection for a memory system
Lance W. Dover, Fair Oaks, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 13, 2023, as Appl. No. 18/351,982.
Claims priority of provisional application 63/371,847, filed on Aug. 18, 2022.
Prior Publication US 2024/0061963 A1, Feb. 22, 2024
Int. Cl. G06F 21/79 (2013.01); G06F 21/60 (2013.01)
CPC G06F 21/79 (2013.01) [G06F 21/602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller configured to couple with a memory system, wherein the controller is configured to cause the apparatus to:
generate, at a host system for the memory system, a command to update or override a protection attribute of a first set of memory cells of the memory system, wherein each of a plurality of sets of memory cells of the memory system is associated with a respective set of one or more first cryptographic keys;
encrypt, at the host system for the memory system, at least a portion of the command based at least in part on a second cryptographic key associated with the host system, the second cryptographic key corresponding to a first cryptographic key within the respective set of one or more first cryptographic keys associated with the first set of memory cells; and
transmit, after encrypting at least the portion of the command at the host system, the command to update the protection attribute of the first set of memory cells.