US 12,468,813 B2
Sequencer firmware calls during radar ramp scenario
Bernhard Greslehner-Nimmervoll, Hagenberg (AT); and Rainer Findenig, Linz (AT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jul. 28, 2023, as Appl. No. 18/360,903.
Prior Publication US 2025/0036768 A1, Jan. 30, 2025
Int. Cl. G06F 21/57 (2013.01); G06F 21/52 (2013.01)
CPC G06F 21/572 (2013.01) [G06F 21/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A radar semiconductor chip, comprising:
a ramp signal generator configured to generate a frequency-modulated ramp signal comprising a plurality of frequency ramps of a ramp scenario, wherein the ramp signal generator is configured to generate the plurality of frequency ramps according to a plurality of ramp parameters, and wherein the ramp signal generator is configured to generate each frequency ramp with a predetermined time dependency relative to each other frequency ramp of the plurality of frequency ramps;
a first memory configured to store a sequencing program associated with generating the frequency-modulated ramp signal, wherein the sequencing program includes a plurality of ramp opcodes that defines the plurality of frequency ramps and a firmware opcode configured to trigger a firmware call, and wherein each ramp opcode of the plurality of ramp opcodes defines a respective timing for a respective frequency ramp such that the predetermined time dependency for each frequency ramp relative to the other frequency ramps of the plurality of frequency ramps is maintained;
a second memory configured to store a firmware program corresponding to the firmware opcode of the sequencing program;
a sequencer configured to read the sequencing program from the first memory, derive control values for the plurality of ramp parameters based on the plurality of ramp opcodes, provide the control values to the ramp signal generator, and provide a start signal to start an execution of the firmware call in response to reading the firmware opcode in the sequencing program; and
a central processing unit (CPU) configured to receive the start signal from the sequencer and, in response to the start signal to start the execution of the firmware call, execute the firmware program from the second memory in parallel to the ramp signal generator generating the frequency-modulated ramp signal,
wherein the ramp signal generator is configured to receive the control values and generate the plurality of frequency ramps based on the control values.