| CPC G06F 15/167 (2013.01) [G06F 15/17 (2013.01); G06F 15/17306 (2013.01); G06F 13/38 (2013.01)] | 19 Claims |

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1. A signal processing device comprising:
a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme, and to perform signal processing of the received first message;
a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme, and to perform signal processing of the received second message; and
a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor, wherein
the first processor comprises a first manager including a first cache for inter-processor communication (IPC); and
the second processor comprises a second manager including a timer and a second cache for the IPC.
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18. A signal processing device comprising:
a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme, and to perform signal processing of the received first message;
a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme, and to perform signal processing of the received second message;
a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor;
a first memory including an IPC channel; and
a second memory storing sensor data including vehicle speed data,
wherein the shared memory is comprised in the first memory.
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19. A vehicle communication device comprising a signal processing device,
wherein the signal processing device comprises:
a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme, and to perform signal processing of the received first message;
a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme, and to perform signal processing of the received second message; and
a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor, wherein
the first processor comprises a first manager including a first cache for inter-processor communication (IPC); and
the second processor comprises a second manager including a timer and a second cache for the IPC.
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