US 12,468,655 B2
Configurable bus park cycle period
Nakul Manjunath, Bangalore (IN); and Richard Nouri, San Diego, CA (US)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 15, 2024, as Appl. No. 18/442,723.
Prior Publication US 2025/0265218 A1, Aug. 21, 2025
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4291 (2013.01) 20 Claims
OG exemplary drawing
 
1. A principal device comprising:
a protocol controller coupled, via a serial bus, to one or more subordinate devices, wherein the serial bus includes a clock wire and a data wire, and wherein the protocol controller is configured to:
send, on the data wire, a read command addressed to a subordinate device to initiate a read transaction;
modify a clock signal on the clock wire to extend a bus park cycle period, the bus park cycle period extended based on a data preparation delay associated with the subordinate device;
subsequent to the bus park cycle period, read data from the data wire during the read transaction;
send, on the data wire, a second read command addressed to a second subordinate device to initiate a second read transaction;
modify the clock signal on the clock wire to extend a second bus park cycle period; and
subsequent to the second bus park cycle period, read second data from the data wire during the second read transaction.