US 12,468,652 B2
Serial peripheral interface compatibility extension switching method and embedded system using the same
Shu-Ming Xu, Hsinchu (TW)
Assigned to GENERALPLUS TECHNOLOGY INC., Hsinchu (TW)
Filed by Generalplus Technology Inc., Hsinchu (TW)
Filed on Dec. 7, 2022, as Appl. No. 18/076,624.
Claims priority of application No. 111116076 (TW), filed on Apr. 27, 2022.
Prior Publication US 2023/0350837 A1, Nov. 2, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 13/10 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 13/102 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An embedded system, comprising:
a master central process unit, comprising a first serial peripheral interface port, wherein the serial peripheral interface port comprises:
a SPI MOSI terminal;
a SPI MISO terminal;
a SPI clock terminal; and
a SPI enable terminal; and
a SPI peripheral device, comprising:
a SPI microcontroller, comprising at least a first serial peripheral interface port, wherein the first serial peripheral interface port comprises:
a first SPI MOSI terminal, coupled to the SPI MOSI terminal of the master central process unit;
a first SPI MISO terminal, coupled to the SPI MISO terminal of the master central process unit;
a first SPI clock terminal, coupled to the SPI clock terminal of the master central process unit; and
a first SPI enable terminal, coupled to the SPI enable terminal of the master central process unit;
wherein the master central process unit is operated at a first operational clock, and the SPI microcontroller is operated at a second operational clock,
wherein the SPI microcontroller is initially configured as a master device operating at a second operational clock, and the master central process unit is initially configured as a slave device;
when the master central process unit in a reset period sends a reset signal to the SPI microcontroller, the master central process unit coercively sets at least one of the SPI MOSI terminal, the SPI MISO terminal, and the SPI clock terminal to a first logic voltage in order to switch the SPI microcontroller to slave mode,
when the first SPI enable terminal of the SPI microcontroller is disabled, and the SPI microcontroller detects that at least one of the first SPI MOSI terminal, the first SPI MISO terminal and the first SPI clock terminal is at the first logic voltage, the first serial peripheral interface port of the SPI microcontroller is reconfigured to operate in slave mode, such that the SPI microcontroller receives data from the SPI MOSI terminal of the master central process unit according to the first operational clock of the master central process unit.