US 12,468,644 B2
Invalidation of permission information stored by another processor
Gaurav Garg, San Jose, CA (US); Bernard J. Semeria, Palo Alto, CA (US); James Vash, San Ramon, CA (US); Jeff Gonion, Campbell, CA (US); Richard F. Russo, San Jose, CA (US); Peter A. Lisherness, Los Gatos, CA (US); Roy G. Moss, Palo Alto, CA (US); and Rohit K. Gupta, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 13, 2024, as Appl. No. 18/742,597.
Claims priority of provisional application 63/627,495, filed on Jan. 31, 2024.
Prior Publication US 2025/0245179 A1, Jul. 31, 2025
Int. Cl. G06F 13/28 (2006.01); G06F 12/1027 (2016.01)
CPC G06F 13/28 (2013.01) [G06F 12/1027 (2013.01); G06F 2212/68 (2013.01); G06F 2213/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
primary processor circuitry that includes an execution pipeline; and
secondary processor circuitry that includes:
translation lookaside buffer circuitry that includes multiple entries configured to store translation information, wherein a given entry includes first-level permission information;
permission circuitry configured to store second-level permission information specified by the primary processor circuitry; and
wherein:
the secondary processor circuitry is configured to determine whether a given memory access is permitted based on both the first-level permission information and the second-level permission information;
the primary processor circuitry is configured to send, based on execution of a remote-permission-table-invalidate instruction by the execution pipeline, a permission invalidate command to the secondary processor circuitry; and
the secondary processor circuitry is configured to, in response to the permission invalidate command, invalidate one or more entries in the permission circuitry that store second-level permission information.