US 12,468,631 B2
Region aware delta prefetcher
Swaraj Sha, Bangalore (IN); Anant Vithal Nori, Bangalore (IN); Sreenivas Subramoney, Bangalore (IN); Stanislav Shwartsman, Haifa (IL); Pavel I. Kryukov, Moscow (RU); and Lihu Rappoport, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2021, as Appl. No. 17/561,831.
Prior Publication US 2023/0205699 A1, Jun. 29, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 9/38 (2018.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0877 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 9/3816 (2013.01); G06F 12/0811 (2013.01); G06F 12/0877 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
memory circuitry including a first data structure; and
prefetch circuitry coupled to the memory circuitry, the prefetch circuitry to:
store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program, the first subregion entry to include a plurality of delta values, a first delta value of the plurality of delta values representing a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region;
detect a first memory access of a first cache line in the first subregion;
select the first delta value based on the first delta value being one of a number of most frequently occurring delta values of the plurality of delta values in the first subregion entry;
identify prefetch candidates based on the first cache line and the first delta value and on the first cache line and one or more other selected delta values of the plurality of delta values; and
issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.