US 12,468,628 B2
Systems and methods for synchronous cell switching for scalable memory
Byung Hee Choi, Fremont, CA (US); and Changho Choi, San Jose, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 16, 2023, as Appl. No. 18/211,131.
Claims priority of provisional application 63/465,794, filed on May 11, 2023.
Prior Publication US 2024/0378149 A1, Nov. 14, 2024
Int. Cl. G06F 12/0815 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a group of memory resources comprising a first memory node and a second memory node, the first memory node being connected to the second memory node over a switching fabric; and
a synchronous clock source connected to the first memory node and the second memory node, the synchronous clock source being configured to generate a synchronized clock signal based on a reference clock signal, and provide the synchronized clock signal to the first memory node and the second memory node to synchronize the first memory node with the second memory node,
wherein the first memory node and the second memory node are configured to encode memory data and decode encoded memory data using the synchronized clock signal received from the synchronized clock source.