US 12,468,627 B2
Address mapping table compression
David Aaron Palmer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 15, 2024, as Appl. No. 18/443,005.
Claims priority of provisional application 63/486,378, filed on Feb. 22, 2023.
Prior Publication US 2024/0281374 A1, Aug. 22, 2024
Int. Cl. G06F 12/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/0646 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0292 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more memory devices; and
a controller coupled with the one or more memory devices and configured to cause the apparatus to:
determine, for a region of an address mapping table that comprises physical addresses and that indicates mappings between the physical addresses and logical addresses, sets of sequentially indexed logical addresses that are mapped to sets of sequentially indexed physical addresses;
select a compression factor for the region based at least in part on the sets of sequentially indexed logical addresses, the compression factor indicating a quantity of physical addresses to be removed per set of sequentially indexed physical addresses; and
remove subsets of physical addresses from the sets of sequentially indexed physical addresses in the region according to the compression factor.