US 12,468,596 B2
Temporal buffering of integrity comparison data
Eric N. Anderson, Marion, IA (US); Matthew P. Corbett, Mount Vernon, IA (US); Jason R. Owen, Marion, IA (US); and Russ D. Uthe, Ely, IA (US)
Assigned to Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed by Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed on Apr. 18, 2024, as Appl. No. 18/639,573.
Prior Publication US 2025/0328408 A1, Oct. 23, 2025
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/16 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/0721 (2013.01); G06F 11/1608 (2013.01); G06F 11/1629 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system-on-chip comprising:
one or more application processing cores with a first instruction set architecture, wherein the one or more application processing cores are configured to execute an integrity application and one or more safety critical applications, wherein the integrity application is configured to generate one or more integrity application outputs;
one or more integrity processing cores with a second instruction set architecture, wherein the first instruction set architecture and the second instruction set architecture are different, wherein the one or more integrity processing cores are configured to execute an integrity monitor, wherein the integrity monitor is configured to generate one or more integrity monitor outputs, wherein the integrity monitor is configured to compare the one or more integrity application outputs and the one or more integrity monitor outputs to detect one of a valid-compare or a mis-compare; and
an integrity memory;
wherein the one or more application processing cores and the one or more integrity processing cores are asynchronized, wherein the integrity memory is configured to provide temporal buffering between the one or more integrity application outputs and the one or more integrity monitor outputs when the integrity monitor compares the one or more integrity application outputs and the one or more integrity monitor outputs.