US 12,468,590 B2
Adaptive wear leveling for endurance compensation
Charles See Yeung Kwong, Redwood City, CA (US); Seungjune Jeon, Santa Clara, CA (US); Wei Wang, Dublin, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 23, 2024, as Appl. No. 18/672,635.
Application 18/672,635 is a continuation of application No. 17/858,731, filed on Jul. 6, 2022, granted, now 12,026,042.
Claims priority of provisional application 63/347,919, filed on Jun. 1, 2022.
Prior Publication US 2024/0320077 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 11/008 (2013.01); G06F 11/073 (2013.01); G06F 2201/81 (2013.01); G06F 2212/7211 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a first block of a set of blocks of the memory device;
identifying, among a plurality of dies of the memory device, a die on which the first block resides;
selecting, from a range associated with a projected reliability metric of the die, a threshold value associated with the die, wherein the range is defined by a minimum value and a maximum value that are correlated to the projected reliability metric of the die; and
responsive to determining that an endurance metric value associated with the die matches the threshold value, performing a programming operation with respect to a second block of the set of blocks.