US 12,468,533 B2
Instruction execution control apparatus and method using correspondence information between different processor instruction sets
Hitoshi Hamao, Tokyo (JP); and Koichi Sato, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Oct. 2, 2023, as Appl. No. 18/479,320.
Claims priority of application No. 2022-182578 (JP), filed on Nov. 15, 2022.
Prior Publication US 2024/0160450 A1, May 16, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3017 (2013.01) [G06F 9/3861 (2013.01); G06F 9/3877 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A non-transitory computer readable storage medium storing a program for causing a computer to:
acquire correspondence information in which a common instruction executable by both a first processor and a second processor is associated with a non-common instruction that is an instruction not executable by the first processor but executable by the second processor;
in a case where the non-common instruction is detected in the first processor, specify the common instruction associated with the non-common instruction in the correspondence information and causing the first processor to execute the specified common instruction, and cause the first processor to execute the common instruction associated with the non-common instruction in the correspondence information in an exception handler executed in response to the detection of the non-common instruction in the first processor; and
determine, in the exception handler, that a next instruction to be executed next to an instruction that has caused the exception handler to be executed is the non-common instruction and causing the first processor to execute the common instruction associated with the next instruction in the correspondence information.