US 12,468,532 B1
Prefetcher circuit with dynamic trigger point
Rustam Miftakhutdinov, Hillsboro, OR (US); and Douglas C. Holman, San Francisco, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,256.
Claims priority of provisional application 63/585,850, filed on Sep. 27, 2023.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30047 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor circuit configured to execute an instruction stream, the processor circuit including:
an instruction cache;
a call stack having entries configured to store an indication of functions that are called within the instruction stream; and
a correlation prefetcher circuit configured to:
in response to detection of an instruction cache miss at a particular point in the instruction stream, determine a depth of a deepest function, of a sequence of functions, that remains in the call stack over an interval preceding the instruction cache miss, the depth being measured based on a position of entries stored in the call stack;
select a trigger point based on the determined depth;
select a training signature based on the selected trigger point; and
in response to subsequently detecting the training signature, generate a prefetch request to prefetch instructions into the instruction cache.