US 12,468,483 B2
Flash memory controller, storage device, and address mapping method of flash memory controller
Chien-Ting Lin, Hsinchu County (TW); Wei-Chi Hsu, Taoyuan (TW); and Chin-Hung Liu, Hsinchu County (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Feb. 19, 2024, as Appl. No. 18/581,353.
Claims priority of application No. 112117298 (TW), filed on May 10, 2023.
Prior Publication US 2024/0377984 A1, Nov. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A flash memory controller, coupled between a host device and a flash memory, comprising:
a specific buffer, for allocating a cache space to cache and temporarily store data stored by the flash memory externally coupled to the flash memory controller; and
a processing circuit, coupled to the specific buffer, for receiving a specific host address from the host device, reading and loading a corresponding address pointer mapping table from the flash memory into the cache space of the specific buffer according to address information pointed by a specific address pointer linker corresponding to the specific host address, determining a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reading and loading a corresponding address mapping table from the flash memory into the cache space of the specific buffer according to address information pointed by the specific address pointer, and for finding and obtaining a specific flash memory address from the corresponding address mapping table according to the specific host address so as to perform an access operation according to the found specific flash memory address;
wherein the processing circuit employs an address pointer linker mapping table having N address pointer linkers, the address pointer linker mapping table is resident and stored in the cache space of the specific buffer, the N address pointer linkers respectively correspond to N portions of a memory space allocated by the flash memory, and the processing circuit determines the specific address pointer linker corresponding to the specific host address from the N address pointer linkers temporarily stored by the specific buffer.