US 12,468,464 B2
Read performance techniques for time retention
Bo Zhou, Shanghai (CN); and Qilin Pan, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 8, 2024, as Appl. No. 18/766,256.
Application 18/766,256 is a continuation of application No. 17/726,255, filed on Apr. 21, 2022, granted, now 12,050,794.
Claims priority of provisional application 63/212,462, filed on Jun. 18, 2021.
Prior Publication US 2025/0013374 A1, Jan. 9, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 1/28 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 1/28 (2013.01); G06F 3/0614 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
perform a respective first read operation on a respective page of each block of a plurality of blocks of the one or more memory arrays;
map each block of the plurality of blocks to a respective bin of a plurality of bins in response to performing the respective first read operations on the respective pages, wherein each bin is associated with a respective set of one or more read voltage offsets; and
perform one or more second read operations on one or more blocks of the plurality of blocks, the one or more second read operations using the respective sets of one or more read voltage offsets associated with the respective bins to which the one or more blocks are mapped.