| CPC G06F 3/0614 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |

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1. A device, comprising:
memory cells; and
a logic circuit configured to store first data in the memory cells and store second data indicative of a pattern of bits in the first data, wherein the first data includes a plurality of bits added to constrain the pattern of bits in the first data.
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