US 12,468,449 B2
Apparatus with response completion pacing
Ying Huang, Boise, ID (US); and Mark Ish, San Ramon, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 28, 2024, as Appl. No. 18/759,793.
Application 18/759,793 is a continuation of application No. 18/049,973, filed on Oct. 26, 2022, granted, now 12,050,776.
Claims priority of provisional application 63/347,929, filed on Jun. 1, 2022.
Prior Publication US 2024/0354006 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a ready response queue configured to store data;
a processing logic operably coupled to the ready response queue and configured to:
track a duration for sending command responses to a device;
determine a target number of responses in the ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue; and
send a response from the ready response queue to the device based on the duration and a number of responses in the ready response queue relative to the target number of responses.