US 12,468,447 B2
Efficiency for consecutive read operations
Giuseppe Cariello, Boise, ID (US); and Fulvio Rori, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 23, 2024, as Appl. No. 18/420,479.
Claims priority of provisional application 63/483,395, filed on Feb. 6, 2023.
Prior Publication US 2024/0264745 A1, Aug. 8, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the apparatus to:
receive a first command indicating a first read operation in a block of memory cells, wherein each memory cell of the block of memory cells is configured to store more than one bit;
apply, based at least in part on receiving the first command, a voltage to a plurality of access lines associated with the block of memory cells to initiate a performance of the first read operation;
receive, after receiving the first command, a second command indicating a second read operation in the block of memory cells, the second command comprising a first indication to refrain from discharging the plurality of access lines, wherein a single bit in the second command comprises the first indication to refrain from discharging the plurality of access lines; and
initiate, based at least in part on receiving the second command, the performance of the second read operation without discharging the plurality of access lines based at least in part on the second command comprising the first indication to refrain from discharging the plurality of access lines.