US 12,468,445 B2
Coordinated in-module RAS features for synchronous DDR compatible memory
Mu-Tien Chang, Santa Clara, CA (US); Dimin Niu, Sunnyvale, CA (US); Hongzhong Zheng, Los Gatos, CA (US); Sun Young Lim, Gyeonggi-Do (KR); Indong Kim, Kyunggi-Do (KR); and Jangseok Choi, San Jose, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 9, 2024, as Appl. No. 18/408,558.
Application 18/408,558 is a continuation of application No. 17/713,228, filed on Apr. 4, 2022, granted, now 12,032,828.
Application 17/713,228 is a continuation of application No. 16/819,032, filed on Mar. 13, 2020, granted, now 11,294,571, issued on Apr. 5, 2022.
Application 16/819,032 is a continuation of application No. 15/213,386, filed on Jul. 18, 2016, granted, now 10,592,114, issued on Mar. 17, 2020.
Claims priority of provisional application 62/347,569, filed on Jun. 8, 2016.
Claims priority of provisional application 62/303,352, filed on Mar. 3, 2016.
Claims priority of provisional application 62/303,349, filed on Mar. 3, 2016.
Claims priority of provisional application 62/303,347, filed on Mar. 3, 2016.
Claims priority of provisional application 62/303,343, filed on Mar. 3, 2016.
Prior Publication US 2024/0143173 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 5/04 (2006.01); G11C 11/406 (2006.01); G11C 29/04 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0652 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/106 (2013.01); G11C 29/52 (2013.01); G11C 5/04 (2013.01); G11C 11/40611 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a controller, a command using an interface, the interface comprising a connection based on an in-line memory module terminal configuration to provide status information of a memory array; and
controlling, by the controller, the interface to provide the status information using the interface based on a result of a correction operation of the memory array.