US 12,468,334 B2
Clock signal realignment for emulation of a circuit design
Alexander Rabinovitch, Shrewsbury, MA (US); Manish Shroff, Milford, MA (US); and Baijayanta Ray, Bangalore (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jul. 21, 2022, as Appl. No. 17/870,374.
Claims priority of application No. 202141033655 (IN), filed on Jul. 27, 2021.
Prior Publication US 2023/0035693 A1, Feb. 2, 2023
Int. Cl. G06F 30/3312 (2020.01); G06F 1/12 (2006.01); G06F 30/20 (2020.01); G06F 30/347 (2020.01); G06F 30/398 (2020.01)
CPC G06F 1/12 (2013.01) [G06F 30/3312 (2020.01); G06F 30/20 (2020.01); G06F 30/347 (2020.01); G06F 30/398 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a circuit design, the circuit design comprising clock signals, wherein each of the clock signals is a data path clock signal;
determining, by a processor, that a first clock signal of the clock signals is faster than a second clock signal of the clock signals;
generating realigned clock signals by aligning rising edges and falling edges of the second clock signal with rising edges of the first clock signal based on determining that the first clock signal is faster than the second clock signal and aligning rising edges of a third clock signal of the clock signals with even cycles of an emulation clock signal, wherein the first clock signal is faster than the third clock signal and the third clock signal is faster than the second clock signal; and
emulating the circuit design using the realigned clock signals.